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BU9883FV-W
Datasheet
○ When the command just before Current Read cycle is Random Read cycle or Current Read cycle (each including
Sequential Read cycle), data of incremented last read address (n)-th address, i.e.n, data of the (n+1)-th address is output.
When the command just before Current Read cycle is Byte Write or Page write, data of latest write address is output.
○ Current Read operation allows the master to access data word stored in internal address counter which is appointed by
P1, P0 bit. This operation involves a two-step process. This device will respond with an acknowledge and then transmit the
8-data bits stored at the addressed location.
If the master does not acknowledge the transmission but does generate the stop condition, at this point this device
discontinues transmission.
note)If the master send Acknowredge at after D0 output, Sequential Read is selected, and this device output next address data, and master can't send stop
condition, so master can't discontinues transmission.
To stop read command, the master must send no Acknowledge at after D0 output, and issue stop condition.
SDA
LIN
S
T
A
R
T
SLAVE
ADDRESS
1 0 1 0 0 P1 P0
R
E
A
D
D7
DATA(n)
D0
D7
DATA(n+x）
D0
S
T
O
P
WPB
Figure 43. SEQUENTIAL READ CYCLE TIMING （ PORT0 ）
○ During the sequential read operation, the internal address counter of this device automatically increments with each
acknowledge received ensuring the data from address will be followed with the data from n+1. For read operations, all bits
of the address counter are incremented allowing the entire array to be read during a single operation. When the counter
reaches the top of the array, it will “roll over” to the bottom of the array of BANK and continue to transmit the data.
○ The sequential read operation can be performed with both current read and random read.
● PORT1,2,3 access commands
If the master access send commands by port1,2,3, WPB pin must be “L”.
S
T
A
R
T
SLAVE
ADDRESS
W
R
I
T
E
1st WORD
ADDRESS(n)
S
T
A
R
T
SLAVE
ADDRESS
R
E
A
D
DATA(n)
S
T
O
P
SDA
LINE
1 0 1
0
0 0
0
WA7
WA0
1 0
1 0
0 0
0
D7
D0
R
/
W
A
C
K
A
C
K
R A
/ C
W K
A
C
K
WPB
Figure 44. RANDOM READ CYCLE TIMING （ PORT1 to 3 ）
○ Random read operation allows the master to access any memory location of the BANK which is appointed by P1, P0.
This operation involves a two-step process.
First, the master issues a write command which includes the start condition and the slave address field (with R/W set to
“0”) followed by the address of the word be read.
This procedure sets the internal address counter of this device to the desired address.
After the word address acknowledge is received by the master, the master immediately reissues a start condition followed
by the slave address field with R/W the set to “1.”
This device will respond with an acknowledge and then transmit the 8-data bits stored at the addressed location. If the
master does not acknowledge the transmission but does generate the stop condition, at this point this device
discontinues transmission.
S
T
A
R
T
SLAVE
ADDRESS
R
E
A
D
DATA
S
T
O
P
SDA
LINE
1
0 1 0
0
0 0
D7
D0
R
/
W
A
C
K
A
C
K
WPB
Figure 45. CURRENT READ CYCLE TIMING （ PORT1 to 3 ）
www.rohm.com
? 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
17/25
TSZ02201-0R2R0G100420-1-2
31.AUG.2012 Rev.001
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